ECC systems are used in a variety of applications including data storage systems and digital communication. Commonly, ECC systems use low-density parity check (“LDPC”) codes or Bose Chaudhuri Hocquengheim (“BCH”) codes. LDPC codes are block codes which use probability-based repeated calculations for error correction. LDPC codes exhibit excellent performance, which has been reported to approach the Shannon limit, a theoretical limit of code performance. BCH codes and other Hamming codes are hard decision codes which enable precise control over the number of bit errors that are correctable by the code. BCH codes can be designed to correct multiple bit errors and have been shown to reliably correct a certain number of errors. However, in order to provide a sufficient level of error correction for a system, the decoder in traditional ECC systems requires a large amount of computational power. Reduction of the power required by the system to successfully decode transmitted data is possible by implementing changes in the decoder.
ECC systems are designed to detect and correct the expected errors to be encountered in the systems they operate within. In particular, in storage devices that employ NAND flash memory, the specific error characteristics of those memory devices must be taken into account. For instance, it is well known that NAND flash memory cells must be first erased before data can be written to them (writing is known as programming in NAND flash technology). The cells are known to have a limited lifetime in terms of the number of Program/Erase (P/E) cycles they are subjected to. Further, the more P/E cycles the cells have been subjected to, the greater likelihood that errors occur when reading data that has been previously written. It is also well-known that the writing of data involves storing a charge on a floating gate in the memory cell. Over time, this charge may leak away, or may be disturbed by the subsequent erasing, reading, or writing of data to neighboring cells. This means that the longer the data has been retained or stored in the cell, the more likely that the charge leaks or is otherwise disturbed, with the result that it becomes increasingly likely that errors occur when the data is subsequently read, as the charge value is not the same as that which was originally stored. These error characteristics have also worsened with the advent of multilevel cell (MLC), triple level cell (TLC) and quadruple level cell (QLC) memory technology, with reduced capability of P/E cycles and retention time.
Over the lifetime of a memory device using NAND flash memory therefore, the rate of errors occurring increases considerably, possibly by several orders of magnitude. In order to cope with the high error rates encountered towards the end of the lifetime of NAND flash memory and in particular with MLC, TLC and QLC type memories, the more capable error correction codes such as LDPC codes are commonly employed. An ECC system designed to cope with the worst case of high error rates at the end of life, would, however, be operating very inefficiently with un-necessarily high power consumption during a large period of the lifetime where error rates are low.
Improvements to ECC systems which lower the energy consumption are particularly sought after, as many traditional ECC systems consume large amounts of processing power. Traditional ECC systems access memory where variables related to the decoding algorithms used in the ECC system are stored, with large power requirements. For example, LDPC code has high throughput but in using an iterative decoding process requires significant computation resources and has high energy consumption compared to other types of ECC systems. Development of low energy-consuming ECC systems is critical for implementation of ECC systems in mobile or portable devices, data centers, or in “green” computing.
One solution to this may be to employ two ECC decoders, the first a low power, low error correcting capability decoder, and the second a higher power, high error correcting capability decoder. However a further complication is that there is also a wide variation in error rates between individual flash memory dies, between flash memory blocks within a die, and between flash memory pages within a block. A two decoder system which simply switches between the two decoders may not be able to operate efficiently without a means to correctly select and switch between the decoders according to the encountered error rate.
Other methods of improving the energy efficiency of the ECC system include reducing the computational work to decode a unit of data or decreasing issues in the auxiliary circuitry implementation. Layered decoding, turbo decoding, iteration control and use of simpler decoding algorithms have been used to attempt to increase energy efficiency on ECC systems.
In another example of attempts to increase energy efficiency of ECC systems, gear-shift decoding has been suggested as a mechanism by which to lower the power consumption of decoding. Gear-shift decoders change their update rules over the course of decoding a single frame. These decoders may start with simple update rules which sequentially proceed to more complex rules for energy efficiency purposes. However, optimization of the scheduling of the rule is complicated and the complex rules consume large amounts of power.
Low power consumption decoding methods must be developed in order to provide decoding for mobile devices and services and data centers. Decoding systems which have high throughput, however, often have high power requirements and current methods for lowering the power consumption of such system are insufficient. In addition, systems employing two or more decoders cannot react sufficiently quickly to error rates which vary widely both instantaneously and over longer periods of time.